As state-of-the-art computer systems and circuits evolve, there is a continuing need for higher performance bipolar junction transistors capable of operating at higher switching speeds, with increasing degrees of device integration, and with a low rate of failure. There is also a continuing need to shrink or scale down device size to obtain improved device performance. In order to obtain further advances in device scaling, improved lithographic techniques and equipment must be developed. Unfortunately, the lithographic patterning tolerances of state-of-the-art equipment are rapidly reaching their limits. The range of future device geometries and contact line widths require extremely small dimensions. Thus, lithographic errors within the normal tolerance range can impede efforts to further shrink device size. Accordingly, it would be advantageous to develop a process and device geometry less dependent on photolithographic accuracy.
Reduced geometry devices can be fabricated using "self-aligned" process techniques. In a self-aligned process, at least one device region is used as an alignment guide for forming a subsequent region(s). Accordingly, self-aligned fabrication processes are less-dependent upon precise photolithographic alignment than similarly directed non self-aligned processes.
Examples of bipolar transistors formed having one or more self-aligned active regions, and requiring one or more critical alignment steps, can be found in U.S. Pat. No. 4,101,350 to Possley, et al. entitled Self-Aligned Epitaxial Method for the Fabrication of Semiconductor Devices; in U.S. Pat. No. 4,531,282 to Sakai, et al. entitled Bipolar Transistor Having Vertically Arrayed Collector-Base-Emitter with Novel Polycrystalline Base Electrode Surrounding Island Emitter and Method of Making the Same; in a publication entitled A 20ps Si Bipolar IC Using Advanced Super Self-Aligned Process Technology with Collector Ion Implantation by Konaka, et. al. published in the IEEE Transactions on Electron Devices, Vol. 36, No. 7, pp. 1370-1375, July, 1989; in a publication entitled SDX: A Novel Self-Aligned Technique and its Application to High Speed Bipolar LSI's by Yamamoto, et al. published in the IEEE Transactions on Electron Devices, Vol. 35, No. 10, pp. 1601-1608, October, 1988; and in a publication entitled A Submicrometer High-Performance Bipolar Technology., by Chen, et al. published in the IEEE Electron Device Letters, Vol. 10, No. 8, pp. 364-366, August, 1989.
Many other examples of bipolar transistors formed using self-alignment steps can also be found. For example, U.S. Pat. No. 4,927,774 to Welbourn, et al. entitled Self-Aligned Bipolar Fabrication Process, discloses a self-aligned process for forming a walled-emitter transistor.
As is well known to those skilled in the art of integrated circuit design, faster switching speeds can be obtained, in part, by reducing the lateral and vertical size and parasitic components of individual transistors and increasing the degree of integration. Typical parasitics include base resistance, r.sub.b, base-collector capacitance, C.sub.bc, collector resistance, r.sub.c, and collector-substrate capacitance, C.sub.cs. As these parasitic components are reduced, device performance improves because faster device operation and lower power consumption is possible.
Attempts have been made at forming bipolar transistors with reduced base and collector resistance (r.sub.b, r.sub.c) and base-collector capacitance (C.sub.bc), using self-alignment techniques. For example, U.S. Pat. No. 4,504,332 to Shinada entitled Method of Making a Bipolar Transistor, discloses a partially self-aligned bipolar transistor having a laterally displaced collector contact electrically connected to an embedded extrinsic collector layer. Not all active regions are self-aligned, however, and the ability to obtain reduced collector-substrate capacitance is limited by at least the width of the embedded extrinsic collector layer.
In summary, the art has yet to produce a completely self-aligned bipolar junction transistor with reduced collector-substrate capacitance.